The invention relates to a digital memory circuit that contains at least two areas each having a multiplicity of memory cells, disposed in matrix form in rows and columns, for storing in each case a binary datum. For each column, a primary sense amplifier is provided to sense the datum stored in an addressed cell. A transfer switch, which can be closed by a column selection signal, is provided to put the first core of a two-core local data line, assigned to the relevant primary sense amplifier, at a first logic potential and the second core of the data line at a second logic potential, if the sensed datum has the first binary value, and to put the first core at the second logic potential and the second core at the first logic potential, if the sensed datum has the second binary value. The cores of each local data line are connected via a respective line switch, which can be closed by a line switch through-connect command, to the cores of an assigned two-core master data line, which leads to the input terminals of an individually assigned secondary sense amplifier. Precharge devices are provided in order, prior to a line switch through-connect command, to equalize both cores of all the local data lines to a potential lying between the first and second logic potentials and to equalize both cores of all the master data lines to one of the two logic potentials. The columns of each area of the memory bank form at least two adjacent groups, each of which occupies a dedicated segment of the relevant area. Each local data line is assigned to exactly one segment of exactly one area of the memory bank, and each master data line is assigned to exactly one segment of each area of the memory bank. DRAM memories are a preferred, but not exclusive, field of application of the invention.
In digital data memories, the binary memory cells of each memory bank are often combined in a plurality of separate areas which each have a dedicated set of sense amplifiers, each of which is responsible for a subset of the cells of the relevant area. Usually, the cells of each memory area form a matrix of rows and columns, and each column is assigned a sense amplifier. Each sense amplifier is connected to all the cells of the relevant column via an assigned bit line. Each row can be addressed selectively by activation of an assigned word line. The corresponding activation signal is derived in a word line decoder (row decoder) from the row address of the memory cell to be read. The activation causes each cell of the relevant row to communicate its memory content via the bit line to the sense amplifier assigned to the relevant column, which sense amplifier thereupon generates an amplified signal representing the binary value of the stored datum. This representation, through the closing of a transfer switch individually assigned to the sense amplifier, is then transmitted to an assigned local data line, which can be connected via a line switch to an assigned master data line common to all the memory areas of the bank, in order to transmit the binary representation to a secondary sense amplifier and there to amplify it for the outputting of the datum.
The transfer switches are controlled by column selection signals that are derived by a column decoder from the column address of the memory cells to be read. The column selection signals are jointly fed to all the memory areas.
In many cases, particularly in large memory banks having a very high number of columns in each memory area, the total number n of columns of each area is divided into m adjacent groups, each of which contains k=n/m columns and occupies a corresponding segment of the memory area. Accordingly, the local data lines are also segmented. Each group (that is to say each segment) can in turn be divided into p adjacent subgroups, each of which contains q=k/p columns, in each case all the transfer switches assigned to the sense amplifiers of the same subgroup being driven by a common column selection signal assigned to the subgroup. In order that the data transmitted by the q transfer switches of the respective same subgroup are forwarded separately from one another in these cases, q local data lines are provided along each segment, each of which data lines is connected to exactly one individually assigned transfer switch of each subgroup of the columns of the relevant segment. If q=1, a dedicated column selection signal is generated for each column and thus for each transfer switch.
In accordance with the number m of segments, m bundles of master data lines are provided. Each of the bundles contains q master data lines that are assigned to the q local data lines of a respective segment of all the memory areas.
The bit lines, the local data lines and the master data line usually have two conductors or wires. For this purpose, each primary sense amplifier is configured with a symmetrical output. If the memory cell content that it senses corresponds to a datum of the first binary value, a potential difference whose polarity indicates the binary value of the datum stored in the cell appears at the output of the amplifier. If the cell content corresponds to a datum of the first binary value, then one output terminal of the amplifier goes to a first defined logic potential, and the other output terminal goes to a second defined logic potential. If the cell content corresponds to a datum of the second binary value, then the two logic potentials appear interchanged at the output terminals of the amplifier. Through the closing of the transfer switch with the line switch closed, the output potentials of the sense amplifier are applied to the cores of the assigned local data line and pass via the line switch to the lines of the assigned master data line in order to produce there a potential difference representing the sensed datum. The secondary sense amplifier is therefore configured as a differential amplifier with a symmetrical input. The supply potentials at the base and load ends of the amplifier are symmetrical with respect to the center between the two logic potentials and near one or the other logic potential.
In the quiescent state of the memory circuit, before a read or write mode is initiated, the lines of all the bit lines are equalized to a specific potential, which usually lies in the middle between the two logic potentials. The lines of all the local data lines are likewise equalized to this potential, specifically for the following reason: during the later column selection, the selected transfer switches are indeed closed not only in that memory area which contains the activated word line, but also in all the other memory areas whose bit lines have all maintained the equalization potential. The above-mentioned equalization of the local data lines to exactly this potential avoids unnecessary charging currents in these other memory areas.
In the quiescent state of the memory circuit, the lines of all the master data lines are likewise equalized to a specific potential. One of the two logic potentials is chosen for this second-mentioned equalization potential, specifically that logic potential which corresponds to or approaches the load-side supply potential of the secondary sense amplifiers. This is because the amplifier then remains in the linear region of the amplifier characteristic curve, if the input terminals are driven with the above-mentioned potential difference representing the sensed datum.
Each line switch has a control terminal for the application of a through-connect signal that closes the switch and keeps it closed for the duration of the signal. Before the closing of the line switches and before a transfer switch is closed at any of the primary sense amplifiers, the lines of all the bit lines and all the local data lines are disconnected from the source of their equalization potential; owing to their line capacitance, however, they still retain this potential for the time being.
In the case of memory circuits according to the prior art, all the line switches that are assigned to the same memory area are controlled jointly. Since the row address of an addressed memory cell also identifies the respective memory area, a line switch selecting device according to the prior art operates only depending on the row address decoded in the word line decoder, in order to transmit the through-connect signal simultaneously to all the line switches of the memory area containing the addressed row.
Consequently, if the line switches of a memory area are closed, which usually occurs before the closing of transfer switches in the relevant memory area, both lines of all the local data lines of all the segments of the memory area first go from their equalization potential (still retained until that point), lying in the middle between the two logic potentials, to the equalization potential of the master data lines, which is equal to one of the logic potentials. For this purpose, the source of the equalization potential of the master data lines has to subsequently supply much charging current.
It is accordingly an object of the invention to provide a digital memory circuit having a plurality of segmented memory areas which overcomes the above-mentioned disadvantages of the prior art devices of this general type, which reduces charging current consumption.
With the foregoing and other objects in view there is provided, in accordance with the invention, a digital memory circuit that has at least one memory bank. The memory bank contains at least two areas each having a multiplicity of memory cells, disposed in a matrix form in rows and columns, the memory cells storing in each case a binary datum. Primary sense amplifiers are provided, and one of the primary sense amplifiers is provided for each of the columns. The primary sense amplifiers sense the binary datum stored in an addressed memory cell of the memory cells. A transfer switch is connected to each of the primary sense amplifiers resulting in a plurality of transfer switches. Two-conductor local data lines are provided and each has a first conductor connected to a respective transfer switch of the transfer switches and a second conductor connected to the respective transfer switch. The respective transfer switch receives and is closed by a column selection signal for putting the first conductor, coupled to a respective primary sense amplifier, at a first logic potential and the second conductor at a second logic potential, if the binary datum sensed has a first binary value, and to put the first conductor at the second logic potential and the second conductor at the first logic potential, if the binary datum sensed has a second binary value. Two-conductor master data lines each having conductors are provided. Line switches are provided and a respective line switch is connected between a respective two-conductor master data line and a respective two-conductor local data line. The first and second conductors of the respective two-conductor local data line are connected through the respective line switch to the conductors of the respective two-conductor master data line. The respective line switch receives and is closed by a line switch through-connect command. Secondary sense amplifiers are provided and each has input terminals connected to the conductors of an assigned one of the two-conductor master data lines. Precharge devices are connected to the first and second conductors of all of the two-conductor local data lines for equalizing both of the first and second conductors of the two-conductor local data lines to a potential lying between the first and second logic potentials. The precharge devices are also connected to the two-conductor master data lines to equalize both of the conductors of all of the two-conductor master data lines to one of the first and second logic potentials. The columns of each of the areas of the memory bank form at least two adjacent groups, and each of the adjacent groups occupies a dedicated segment of a relevant area. Each of the two-conductor local data lines is assigned to exactly one of the dedicated segments of exactly one of the areas of the memory bank. Each of the two-conductor master data lines is assigned to exactly one of the dedicated segments of each of the areas of the memory bank. A line switch control device, depending on row and column addresses of the addressed memory cell, transmit the line switch through-connect command only to the line switches connected to the two-conductor local data lines of the dedicated segment containing the addressed memory cell.
The line switch control device according to the invention thus provides for closing of the line switches on only the local data lines which belong to the segment in which a write or read mode takes place. By virtue of the invention, the charging current consumption from the source of the equalization potential of the master data lines is lower than in conventional practice, because not all the local data lines of the relevant memory area are charged to the equalization potential of the master data lines, but rather only the local data lines of a single segment. If each memory area contains m segments, then the charging current consumption is only about 1/m of the charging current consumption to be expected in the case of the prior art.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a digital memory circuit having a plurality of segmented memory areas, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.